1. Field of the Invention
This invention relates to a method of fabricating semiconductor devices and more specifically to a planarization process for use during the fabrication of semiconductor devices.
2. Description of the Prior Art
The minimum feature size in state of the art very large scale integrated circuits ("VLSIs"), such as high density memory chips, microprocessors and the like, has shrunk to the submicron level.
These VLSIs utilize a variety of devices (transistors and other circuit elements) having different feature sizes. Some devices may have submicron feature size while the others may have much greater feature sizes. Also, shallow isolation trenches of constant height and varying widths are used to isolate individual devices. The trench widths can vary greatly. These isolation trenches are typically filled with a dielectric material, such as silicon dioxide. Several VLSI chips are fabricated on a single substrate or wafer and each wafer may require several global planarization and etch-back steps. Because of the complex topography, especially when shallow trenches of greatly varying widths are used, a problem often encountered is achieving a uniform oxide fill in those trenches which is independent of trench size and device density. For such VLSIs, topology management during fabrication has become a critical process step.
Etch-back of a resist-coated dielectric layer has commonly been used to planarize semiconductor wafers. In this technique a single film or layer of a dielectric material such as silicon dioxide is deposited over the wafer surface to be planarized. An organic film like photoresist or polyamide is then spun-on the wafer so as to planarize the entire surface of the wafer. This combination of the spun-on film and dielectric are then etched in a plasma environment that has been set to produce equal amount of etch rates for both the organic and the dielectric films. However, when the distance between features increases, this technique produces a conformal instead of a planar surface.
Another method to obtain better planarization of a silicon wafer having geometry of FIG. 1 and the like is to make the wide trench 23 look like a narrow trench by forming a first layer of photoresist only in the wide trench 2 before spinning-on a second photoresist or polyamide layer on the entire wafer. This process is described in Sheldon et al., "Application of a Two-Layer Planarization Process to VLSI Intermetal Dielectric & Trench Isolation Process," IEEE Transactions on Semiconductors Manufacturing, Vol. 1, No. 4, November, 1988. This method produces better planarization than the conventional method described above, but still is not suitable, especially when the topology includes shallow trenches of varying widths. It is highly desirable to obtain a uniform oxide fill in the trenches which is independent of the trench size and/or pattern density. The present invention, which utilizes a three-layer planarization process instead of the conventional two-layer planarization process, provides uniformly oxide-filled shallow trenches and is substantially independent of the trench sizes and pattern density.